The field of the invention is that of packaging integrated circuits.
In the field of packaging integrated circuits, there is a constant drive to make the packaging more compact, so that more chips per unit of area can be fitted within a given volume.
Various schemes to stack chips vertically have been proposed, but that suffer from various drawbacks. In the particular case of ball grid array contacts, which are preferred in many applications because of superior electrical performance, the vertical height of the chips is an issue, since excessive vertical height must be compensated for by large-diameter balls or by expensive alternatives such as putting down spacer layers to build up the height.
Using a cavity in a printed circuit board has the drawback that the cost of forming a cavity can be excessive in a cost-conscious field such as packaging. Special-configuration boards that are manufactured in limited numbers also suffer from an associated high inventory cost.
Passing signals between vertically separated chips also presents a challenge to achieve reliably and economically.
The invention relates to an integrated circuit package having two parallel printed circuit boards joined together by electrical connections, the upper board having an integrated circuit attached by flip-chip technology on its upper surface and the lower board having an aperture extending through it (cavity) for holding an integrated circuit that is located beneath the upper integrated circuit.
A feature of the invention is the lower integrated circuit being bonded to the bottom of the upper board below the upper integrated circuit and electrically connected to wiring on the lower surface of the lower board by wire bond connections.
Another feature of the invention is the attachment of the two boards by ball grid connectors that also carry electrical signals.
Another feature of the invention is the attachment of the lower surface of the lower board to a support by contacts having a vertical dimension sufficient to provide clearance for the projection of the lower integrated circuit past the lower surface of the lower board.